Field of the Invention
The present invention generally relates to III-V semiconductor Field Effect Transistor (FET) manufacture and more particularly to improving yield and reliability in III-V semiconductor chip manufacture.
Background Description
Semiconductor technology and chip manufacturing advances have resulted in a steady decrease of chip feature size to increase on-chip circuit switching frequency (circuit performance) and the number of transistors (circuit density). Shrinking/reducing device or field effect transistor (FET) feature sizes and, correspondingly, device minimum dimensions, including horizontal dimensions (e.g., minimum channel length) and vertical dimensions (e.g., channel layer depth, gate dielectric thickness, junction depths and etc.), shrinks device size for increased device density and device performance. Device operating conditions including supply voltages and voltage swings reduce correspondingly as chip and device shrink. Generally, all other factors being constant, the active power consumed by a given unit increases linearly with switching frequency, i.e., performance. Thus, notwithstanding the decrease of chip supply voltage, chip power consumption has increased as features shrink and performance improves. Both at the chip and system levels, cooling and packaging costs have escalated as a natural result of this increase in chip power. For low end systems (e.g., handhelds, portable and mobile systems), where battery life is crucial, reducing net power consumption is important but, such a power reduction must come without degrading chip/circuit performance below acceptable levels.
Thus, to minimize semiconductor circuit power consumption, most integrated circuits (ICs) are made in the well-known complementary insulated gate FET technology known as CMOS. A typical CMOS circuit includes paired complementary devices, i.e., an n-type FET (NFET) paired with a corresponding p-type FET (PFET), usually gated by the same signal. Since the pair of devices have operating characteristics that are, essentially, opposite each other, when one device (e.g., the NFET) is on and conducting, the other device (the PFET) is off, not conducting and, vice versa. An ideal on device may be modeled simply as a closed switch and an ideal off device may be modeled as an open switch. Thus, for ideal devices there is no static or DC current path in a typical CMOS circuit. Also, an ideal CMOS circuit consumes no static or DC power, consuming only transient power from charging and discharging purely capacitive loads.
For example, a CMOS inverter is a series connected PFET and NFET pair connected between a power supply voltage (Vdd) and supply return or ground (GND). Both devices are gated by the same input and both drive the same output. The PFET pulls the output high and the NFET pulls the output low at opposite input signal states. Ideally, when the gate of a NFET is below some positive threshold voltage (VT) with respect to its source, the NFET is off, i.e., the switch is open. Above VT, the NFET is on conducting current (Ion), i.e., the switch is closed. Similarly, a PFET is off (Ioff=0) when its gate is above its VT, i.e., less negative, and on below VT. Thus, ideally, the CMOS inverter in particular and CMOS circuits in general pass no static (DC) current. So, ideally, device on to off current ratios (Ion/Ioff) are very large and, ideal CMOS circuits use no static or DC power, consuming only transient power from charging and discharging capacitive loads. In practice, however, typical FETs are much more complex than switches with inherent current path resistances and various parasitic leakage currents.
Consequently, transient power for charging and discharging circuit loads accounts for only a portion (albeit a major portion) of CMOS chip power consumption. FET drain to source current is unidirectional current and so, consumes static or DC power, and depends upon circuit conditions and device transient voltages. Inherent current path resistances, e.g., source/drain and contact resistance, tend to limit drive current and add stage delays, all of which impairs performance.
Also, since device VT is directly proportional to gate dielectric thickness, as FET features (including gate dielectric thickness) shrink, these shorter, lower VT FETs conduct parasitic off currents including what is known as subthreshold current, i.e., when the device gate biases are such that the devices are off. Moreover, for a particular device, subthreshold current increases exponentially with the magnitude of the device's drain to source voltage (Vds) and reduces exponentially with the magnitude of the device's VT. When multiplied by the millions and even billions of devices on a state of the art SRAM, even 100 picoAmps (100 pA) of leakage in each of a million cells, for example, results in chip leakage on the order of 100 milliAmps (100 mA). Thus, as chip features have shrunk, these leakage sources have become more prominent.
While especially for complex chips and arrays with a large number of devices, device leakage (both gate and subthreshold) chip leakage power can be overwhelming, leakage reduction techniques have been equally unpalatable. So unfortunately, especially for III-V semiconductor chip fabrication, leakage and gate dielectric limits have become constraints on circuit performance and chip density.
Thus, there exists a need for improved sub-threshold leakage and reduced contact resistance in semiconductor chips, and more particularly for manufacturing III-V semiconductor chips with low sub-threshold leakage and low source/drain resistance.